Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 100 is shown in FIG. 1. The memory cell 100 comprises a semiconductor substrate 170 of a first conductivity type, such as P type. The substrate 170 has a surface on which there is formed a first region 160 (also known as the source line SL) of a second conductivity type, such as N type. A second region 110 (also known as the drain line or bit line) also of N type is formed on the surface of the substrate 170. Between the first region 160 and the second region 110 is a channel region 180.
A word line 120 (WL) is positioned above a first portion of the channel region 180 and is insulated therefrom. The word line 120 has little or no overlap with the second region 110.
A floating gate 140 (FG) is over another portion of the channel region 180. The floating gate 140 is insulated therefrom, and is adjacent to the word line 120. The floating gate 140 is also adjacent to the first region 160. The floating gate 140 may overlap the first region 160 to provide coupling from the first region 160 into the floating gate 140.
A coupling gate 130 (CG, also known as control gate) is over the floating gate 140 and is insulated therefrom.
An erase gate 150 (EG) is over the first region 160 and is adjacent to the floating gate 140 and the coupling gate 130 and is insulated therefrom. The top corner of the floating gate 140 may point toward the inside corner of the T-shaped erase gate 150 to enhance erase efficiency. The erase gate 150 is also insulated from the first region 160.
The cell 100 is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 100 is as follows. The cell 100 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 150 with other terminals equal to zero volts. Electrons tunnel from the floating gate 140 into the erase gate 150 causing the floating gate 140 to be positively charged, turning on the cell 100 in a read condition. The resulting cell erased state is known as ‘1’ state.
The cell 100 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 130, a medium voltage on the source line 160, a medium voltage on the erase gate 150, and a programming current on the bit line 110. A portion of electrons flowing across the gap between the word line 120 and the floating gate 140 acquire enough energy to inject into the floating gate 140 causing the floating gate 140 to be negatively charged, turning off the cell 100 in read condition. The resulting cell programmed state is known as ‘0’ state.
The programming operation causes substantial stress on memory cell 100. For example, over time, electrons will become trapped in the insulation layer between floating gate 140 and substrate 170 as a result of the hot electron programming mechanism. This electron trapping effect will result in higher voltages being required for erase and programming operations, which results in lower erase efficiency and programming efficiency of memory cell 100.
The prior art includes some attempts to mitigate the degradation caused by programming operations. FIG. 2 depicts a conventional control gate pulse 210 applied to control gate 130 during a programming operation. The peak voltage of control gate pulse 210 ranges between 10 and 11 volts. FIG. 3 depicts a prior art method 300 that attempts to mitigate degradation compared to the method of FIG. 2 by staging the beginning of the control gate voltage 330 applied to control gate 130, the erase gate voltage 340 applied to erase gate 150, the word line voltage 350 applied to word line 120, the voltage differential 320 applied to source line 160, and voltage 310 applied to bit line 110 during a programming operation. The method of FIG. 3 is described in U.S. Pat. No. 8,488,388.
Another prior art method 400 is depicted in FIG. 4. There, a ramped voltage 410 is applied to control gate 130 during a programming operation instead of the control gate pulse 210 of FIG. 2. Prior art method 400 is described in T. Yao, A. Lowe, T. Vermeulen, N. Bellafiore, J. V. Houdt, and D. Wellekens, “Method for endurance optimization of the HIMOS™ flash memory cell,” IEEE 43rd Annual International Reliability Physics Symposium, 2005, pp. 662-663.
These prior art methods have drawbacks. Method 200 does not mitigate degradation caused by peak voltage stress. Method 300 can mitigate degradation at a cost of longer programming time. Method 400 requires additional circuitry to regulate control gate voltage ramp. In addition, the method 400 of FIG. 4 requires greater time for a programming cycle than the method 200 of FIG. 2. For example, in order to utilize ramped voltage effects to mitigate degradation when data require many words/bytes to be programmed by the method 400, one has to ramp voltage up and down each time a word/byte is programmed. As a result, the total data programming time is increased. Additionally, charging and discharging high voltage gate each program cycle can increase power consumption.
What is needed is an improved design that reduces degradation in the memory cell. What is further needed is an improved design that reduces degradation but does not require greater time for programming operations than the conventional method. What is further needed is an improved design that reduces degradation and actually require less time for programming operations than the conventional method.